Enabling a THz Ultra High-Speed Digital Test Ecosystem

Faster networking speeds require faster memory and faster serial bus communications. Peripheral Component Interconnect Express(PCIe) speeds are evolving from PCIe 5.0 to PCIe 6.0 to support these increased speeds. The same is true for memory, as double date rate (DDR) memory evolves from DDR 5.0 to DDR 6.0. Increasing speeds of serial data communications requires precision high-speed testing at every level. Testing at these faster speeds requires full compliance testing to the latest standards. Data center speeds are moving quickly from 100 gigabits per second (Gbps) to 400 Gbps to TeraHz throughputs to support exploding computing and performance demands in the hyperscale network. Multilevel signal modulation technologies, such as 4-level pulse amplitude modulation (PAM4), will enable 400GE & beyond. Scalable, reliable, and high-performance interconnectivity both inside the data center (intra-DCI) and between data centers (inter-DCI) are of paramount importance. In this paper, we will dig deep and discuss on how ultra high speed digital testing enables Tera Hz system designs.