Due to ever-increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with increased inter-symbol interference. It becomes critical to build up an accurate pre-layout model for the bus, testing it against specifications and optimizing it before spinning another PCB layout. To complete the flow, the same analyses can be applied to post-layout memory buses as well. In this webinar, we will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to optimize them to meet design targets.