Pushing the Speed Envelope for Memory System Designs



Memory interface speeds keep increasing to meet performance demand. For instance, DDR5 is 275% faster than DDR4, reaching 8800 MT/s or more. Higher speeds also complicate memory design and validation. To achieve the next memory standard, designers need a connected workflow that streamlines time-to-insight from concept to simulation and test. 


In this webinar, you will learn from industry experts:
  • Best practices pathfinding for complex modulation interfaces.
  • Understand jitter amplification and equalization as speeds increase. 
  • Improve analysis accuracy using probe models to account for equipment loading effects.


Keysight University: Quick Start to DDR5 memory design View/Download
Four Considerations for High-Speed Digital Design Success (eBook) View/Download
ADS SW Trial View/Download


  • Hee Soo Lee
    SerDes Product Owner at Keysight Technologies
    HeeSoo LEE is the SerDes/DDR product owner in the EEsof EDA group of Keysight Technologies DES division, located Santa Rosa California, USA. He has held several different positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard including consulting business manager, technical marketing lead, and field applications engineer since 1989. Before, he worked for Daeryung Ind. Inc. as a RF/MW circuit design engineer. He has over 30 years of design and simulation experience in the area of RF, microwave, and high-speed digital designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.
  • Randy White
    Memory Solutions Program Manager - Keysight Technologies
    Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques, including de-embedding algorithms, measurement/model correlation, high-speed measurements for real-time & sampling oscilloscopes, and BERTs & AWGs. He has participated on many standards committees, including PCI-SIG, USB-IF, SATA-IO, and JEDEC, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.

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Webinar: Pushing the Speed Envelope for Memory System Designs by Keysight