Signal Integrity Simulation Flow for High-Speed Interconnects

This presentation covers Signal Integrity Simulation Flow for Differential High Speeds Interconnects (HSIO) such as PCIe and USB. Three main areas will be discussed:
(i) Channel Design - focusing on getting a “clean” signal on printed circuit board (PCB) including channel optimization techniques. The performance of signal path is evaluated through the time-domain reflection (TDR) impedance plot, understanding of insertion loss as well as the reflection loss of the signal when it travels through the channel.
(ii) End-to-end Simulation using ChannelSim – focusing on the setup of transmitter and receiver buffers using generic IBIS-AMI as well as observation of HSIO signaling margin such as eye height and eye width.
(iii) Transient Simulation – targeting Signal and Power Integrity (SIPI) co-simulation for dual referencing design. The time-domain approach allows power noise injection to the simulation testbench and its noise coupling impact to HSIO will be observed.