Simplify Design Verification and Compliance with Standards-Driven EDA Workflows

About

Innovation and technology discovery are not slowing down. And with every iteration of modern technology comes higher-bandwidth and lower-latency data transmission requirements. From processors using the latest chiplet architecture and UCIe to data centers using PCIe® 6.0, the quality of interconnect communication can make or break the design.

As electronics become denser and interconnects more complex, the design process becomes more challenging. Designers require more automation and cross-functional collaboration to meet stringent industry standards and specifications. This webinar introduces the newest 2024 additions to Keysight EDA: Chiplet PHY Designer and System Designer for PCIe®. You will learn about end-to-end simulation and standards-driven workflows that reduce time to insight, eliminate unnecessary prototype spins, and remove knowledge silos.

Handouts

Application Note: How to Detect Signal Integrity Issues in Chiplet Designs Early View/Download

White Paper: Essential Insights for Design PCIe® 6.0 Interconnects View/Download

Webpage: W3650B Chiplet PHY Designer View/Download

Webpage: W3651B System Designer for PCIe ® View/Download

Presenters

Roberto Piacentini

Senior Product Marketing Manager – High-Speed Digital, EDA Software

Roberto is a senior business leader with over 25+ years of experience in design, test & measurement, and AI spaces. Throughout his career, he held roles in executive management, global marketing operations, and technical R&D. At Keysight, Roberto creates and executes marketing strategies for Electronic Design Automation (EDA) software across high-speed digital, power electronics, and design modeling applications for semiconductor, data center, and consumer electronics industries. He has bachelor’s degrees in electrical engineering and computer science and a master’s in business administration.
Tim Wang Lee

Signal Integrity and Chiplet Application Scientist

Tim Wang Lee is a Signal Integrity Application Scientist and a high-speed digital applications product manager in Keysight Technologies. Tim received his Ph.D. in Electrical Engineering from the University of Colorado at Boulder in 2020. His work focuses on understanding the printed circuit board fabrication process and how it impacts the on-board Signal Integrity. Lately, he has been presenting ways to improve simulation and measurement correlation. Tim has garnered much acclaim for his well-crafted presentations and memorable delivery style.
Saish Sawant

PCIe Application Development Scientist

Saish Sawant is an Application Development Scientist with Keysight Technologies – Keysight EDA business group. He graduated from University of Colorado – Boulder with a focus on RF/Microwave and Signal Integrity. Prior to graduate school, he worked for Society for Applied Microwave Electronics Engineering and Research (SAMEER), a Government of India R&D institute in Mumbai, India as Research Scientist developing RF frontend sub-systems. 
Stephen Slater

Director of Product Management

Stephen Slater leads the product management team for Keysight EDA.  Stephen has over 10 years' experience working with customers in the domain of signal integrity, in multiple applications ranging from EM extraction of PCBs to PCIe, IBIS-AMI and DDR5 memory. Prior to his current role, he was a product manager for HSD solutions in Keysight's Advanced Design System (ADS) software.  Stephen has dual bachelor's degrees in electronic engineering (hons.) & information technology from Griffith University, Australia.