Why Chiplets with UCIe are the Next Big Thing

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About

Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications such as cell phones, autonomous vehicles, etc. 

In this panel session, signal and power integrity experts will discuss:

  • Industry trends and why chiplets with UCIe are the next big thing.
  • Signal and power integrity considerations when integrating chiplets and UCIe interfaces.
  • EDA tools evolved, and how to streamline chiplets integration into the design workflow.

Presenters

  • Hee-Soo Lee
    Product Owner for DDR and SerDes Simulation
    HeeSoo LEE is the SerDes/DDR product owner in the EEsof EDA group of Keysight Technologies DES division, located Santa Rosa California, USA. He has held several different positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard including consulting business manager, technical marketing lead, and field applications engineer since 1989. Before, he worked for Daeryung Ind. Inc. as a RF/MW circuit design engineer. He has over 30 years of design and simulation experience in the area of RF, microwave, and high-speed digital designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.

  • Heidi Barnes
    Power Integrity Product Owner
    Heidi is a senior application engineer in signal and power integrity. Her recent activities include the application of electromagnetic, frequency, transient, and channel simulators to solve signal integrity (SI) and power integrity (PI) challenges. Heidi’s experience includes six years in SI and PI for ATE test fixtures for Verigy, an Advantest Group, six years in RF/Microwave microcircuit packaging for Agilent Technologies, and ten years with NASA in the aerospace industry. She was awarded the 2017 DesignCon Engineer of the Year Award.
  • Randy White
    Memory Solutions Program Manager
    Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques, including de-embedding algorithms, measurement/model correlation, high-speed measurements for real-time & sampling oscilloscopes, and BERTs & AWGs. He has participated on many standards committees, including PCI-SIG, USB-IF, SATA-IO, and JEDEC, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.

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Webinar: Why Chiplets with UCIe are the Next Big Thing by Keysight