High-Speed Interface Design
About this Event
The strong consumer demand for faster internet speed is pushing the High-speed digital interface technology to evolve at a faster rate than ever. Design and development engineers are now facing challenges that are far more complex than before. We will discuss these changes, challenges, and how you may tackle them.

"Register for Series" allows you to have a collection of "Live", "On-demand" webinars with one registration. So that you will have all the valuable information in one go.
This Event Has 6 Sections
  • 9:30 AM SGT (GMT +8) | 28 February, 2023
    Data Center Technologies That Are Shaping the Future of Communication
    Tuesday, February 28, 2023 · 9:30 AM +08
    This session discusses the challenges of network and data center performance while meeting cost and energy consumption targets. We will elaborate on how UCIe builds an ecosystem of chiplets for on-package innovations, and how the IOWN Global Forum will propel technologies in communication and network infrastructure to meet technological challenges and social needs. We will close with an outlook on data center build out and the timelines for 800G and 1.6T deployments.

    Joachim Peerlings, Keysight
    Masahito Tomizawa, Nippon Telegraph and Telephone Corporation
    Gerald Pasdast, Intel Corporation
    Vladimir Kozlov, Lightcounting
  • 11:00 AM SGT (GMT+8) | 28 February, 2023
    Signal Integrity Simulation Flow for High-Speed Interconnects
    Tuesday, February 28, 2023 · 11:00 AM +08
    This presentation covers the Signal Integrity Simulation Flow for High Speed Interconnect (HSIO) which discusses the Channel Design, End-to-end Simulation using ChannelSim and Transient Simulation.

    Presenter: Li Wern Chew, Intel Microelectronics (M) Sdn. Bhd.
  • 1:00 PM SGT (GMT+8) | 28 February, 2023
    Analyzing Memory Bus to Meet with DDR Specifications
    Tuesday, February 28, 2023 · 1:00 PM +08
    With memory getting into the multi-gigabit range, the design margins are tighter due to higher crosstalk between vias and traces. Optimizing your design and testing it against specifications is critical. We will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to design with them.

    Presenter: Hee-Soo Lee, Keysight
  • 2:00 PM SGT (GMT +8) | 28 February, 2023
    DDR5/LPDDR5 - Challenges on Memory Device/System Validation & Solutions
    Tuesday, February 28, 2023 · 2:00 PM +08
    This session will provide an overview of DDR5/LPDDR5 technologies.
    Various challenges on real test environment and JEDEC spec updates will be touched along with Keysight solution for design & validation during the session.

    Presenter: Kar Hooi Kuan, Keysight
  • 9:30 AM SGT (GMT+8) | 1 March, 2023
    Solid PCIe® Protocol Test Strategy Enables Datacenter Transformation
    Wednesday, March 1, 2023 · 9:30 AM +08
    Cloud services enabled by high performance datacenters continue to reach further into our lives, providing us services and insights once thought impossible. While these advances are clear to everyone, behind the scenes, the datacenter itself is undergoing a transformation as compute, storage, and memory resources are dissaggregated. An important technology enabling this disaggregation of datacenter resources is PCIe®. Having clear understanding and insight into how PCIe® is used in the datacenter, and the unique challenges of testing PCIe® protocol, as well as the protocols that leverage PCIe® such as NVMe™ and CXL, will be critical to building products and applications that can be deployed effectively in the disaggregated datacenter. This webinar, "PCIe® Protocol Test enables Datacenter Transformation" will examine how PCIe® is being deployed in the datacenter, and how different PCIe® use cases present protocol test challenges, and how best to address them through a solid PCIe® protocol test strategy.

    Presenter: David Woolf, Keysight
  • 10:30 AM SGT (GMT +8) | 1 March, 2023
    Testing USB4® and Beyond
    Wednesday, March 1, 2023 · 10:30 AM +08
    This webinar will introduce you to the changes and challenges going from USB 3.2 to USB4®. Also an introduction to Next-Gen USB and Type-C® technologies beyond USB4®. Plus other changes with USB-PD. We will show you how to successfully Electrical Test your USB4® products, coupled with pitfalls you can avoid.

    Presenter: Jit Lim, Keysight
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