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Analyzing Memory Bus to Meet with DDR Specifications

About This Webinar

Due to ever-increasing data demand, the speed grade for memory is now getting into the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with increased inter-symbol interference. It becomes critical to build up an accurate pre-layout model for the bus, testing it against specifications and optimizing it before beginning PCB layout. To complete the flow, the same analyses can be applied to post-layout memory buses as well. In this webinar, we will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to modify them to meet design targets.

Key Learnings:
- Defining Pre-layout memory interface bus channel models
- Using Post-layout channel models to get standard compliant
- Leveraging a Wizard-driven smart pre-layout workflow for Data and Command/Address buses

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Featured Presenters
Webinar hosting presenter

Hee-Soo Lee

Product Owner for DDR and SerDes Simulation
HeeSoo LEE is the SerDes/DDR product owner in the EEsof EDA group of Keysight Technologies DES division, located Santa Rosa California, USA. He has held several different positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard including consulting business manager, technical marketing lead, and field applications engineer since 1989. Before, he worked for Daeryung Ind. Inc. as a RF/MW circuit design engineer. He has over 30 years of design and simulation experience in the area of RF, microwave, and high-speed digital designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.

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