Simulating for High-Speed Digital Insights

About This Event

The latest technology for serial links and memory interfaces is getting into the multi-gigabit range. We see them adopting multi-level modulations and more advanced data recovery methods. As a result creating a stable and compliant design is more challenging than ever before and standard signal integrity analysis is no longer sufficient.

Keysight is offering a design flow, which gives you all the insights you need. In this webinar series, our experts will cover leading edge applications of Keysight's premier SerDes and Memory simulation platform, PathWave ADS, with respect to Signal Integrity, Power Integrity and EMI simulation and analysis.
Sessions in this Event
  • February 7, 2023 | 10:00am (GMT +8)
    Perform Simulation-Based, Virtual Compliance Tests for DDR
    Due to ever increasing data rates there is less design margin given to memory design engineers. You will have to make sure that your ... View more
  • Available On-Demand
    Generating AMI Models for SerDes Applications
    AMI (Algorithmic Modeling Interface) is the industry standard for SerDes transmitter and receiver models. It includes equalization, a... View more
  • Available On-Demand
    Simulating PCIe Gen5 for Embedded System Design
    Designers need to balance material selection and PCB fabrication options, together with design strategies for vias, connectors and ch... View more
  • Available On-Demand
    Optimizing Capacitor Selection and Placement for Power Integrity
    Avoid costly retrofits or schedule slippage with multiple re-spins. Start early in the design to select the right capacitors and meet... View more
  • Available On-Demand
    Conducted EMI Simulations Made Easy with PathWave ADS
    The automotive industry applies stringent requirements for EMI with CISPR 25 to avoid disturbances in a vehicle. You will want to cap... View more
  • Available On-Demand
    Analyzing Memory Bus to Meet with DDR Specifications
    With memory getting into the multi-gigabit range, the design margins are tighter due to higher crosstalk between vias and traces. Opt... View more