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Simulating PCIe Gen5 for Embedded System Design
About This Webinar
High-performance computing for embedded system applications is pushing the envelope for speed, a small form-factor, and the right price-point. Designers need to carefully balance material selection and PCB fabrication options, together with smart design strategies for vias, connectors, and PCB trace routing. In this webinar, we will walk through the simulation process that SECO Italy has undertaken to ensure design success.
Key Learnings:
- The benefits of using Standard-Specific PCIe Gen5 Tx and Rx AMI models
- An optimization strategy for differential-vias
- An example of Electromagnetic (EM) simulation of modular PCBs with comparison to prototypes
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Featured Presenters
Signal & Power Integrity Simulation Specialist, SECO SpA
Laura Fabbri is Signal & Power Integrity Designer at SECO company. Laura graduated in 2016 with a M.Sc. in Biomedical Engineering with electronics background and is now an addition to the PCB Design & HW Validation dept. Laura's main focus is High-Speed Digital signals, with her team works on electromagnetic design using Keysight instruments.
Application Engineer and Business Development Manager for High Speed Digital and Power Electronics, Keysight Technologies
Simon’s recent activities include the application of electromagnetic, frequency, transient, and channel simulators to solve Signal Integrity (SI) and Power Integrity (PI) challenges. He works as an Application Engineer and Business Development Manager for High Speed Digital and Power Electronics for Keysight Engineering Design Automation tools since 2018.
His past experience includes 7 years in SI,PI and EMC simulation in the EDA business, leading AE and support teams. Before he worked 2 years on SerDes physical layer design. His previous experience includes 15 years on Memory Module Design and electrical & thermomechanical Simulation of PCB applications, where he contributed to JEDEC for DDR2 and 3 standardizations, responsible for a WW team developing DDR based customized DDR solutions. Simon hold several patents in the field of memory system and bus design.
His past experience includes 7 years in SI,PI and EMC simulation in the EDA business, leading AE and support teams. Before he worked 2 years on SerDes physical layer design. His previous experience includes 15 years on Memory Module Design and electrical & thermomechanical Simulation of PCB applications, where he contributed to JEDEC for DDR2 and 3 standardizations, responsible for a WW team developing DDR based customized DDR solutions. Simon hold several patents in the field of memory system and bus design.
Application Development Engineer – High-Speed Digital Simulation
Saish Sawant is Application Development Engineer with Keysight Technologies - PathWave Software Solutions group. He graduated from University of Colorado – Boulder with focus on RF/Microwave and Signal Integrity. Prior to graduate school, he worked for Society of Applied Microwave Electronics Engineering & Research (SAMEER), a Government of India R&D institute in Mumbai, India as Research Scientist developing RF frontend sub-systems.
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